FIG. 10 is a block diagram which schematically illustrates the whole structure of the apparatus of the above-described type for carrying out serial control.
In FIG. 10, reference numeral 10 designates a machine controller serving as a controller for totally controlling a certain machine for which the apparatus is arranged. Reference numerals 21 to 2n designate sensors or actuators disposed in predetermined locations in the machine. Reference numeral 30 designates a main controller disposed adjacent to the machine controller 10 to serve as central controlling means for the sensors or actuators 21 to 2n. Reference numerals 41 to 4n designate node controllers disposed in correspondence to the respective sensors or actuators 21 to 2n to intermediately process various data (sensor data or actuator control data) between the node controllers 41 to 4n and the main controller 30, respectively. Usually, with such an apparatus for carrying out serial control as described above, the main controller 30 and the node controllers 41 to 4n are serially connected to each other in a loop-shaped configuration, as shown in FIG. 10.
FIGS. 11a-11c illustrate by way of example a plurality of protocols for transmitting a series of signals S0 to Sn between the main controller 30 and the node controllers 41 to 4n in the apparatus of the present invention.
Specifically, according to this example, each of the signals S0 to Sn includes a data row comprising a row of sensor data indicative of a sensor output from each sensor or a row of control data indicative of the content of control for controlling a manner of driving each actuator, a start code for indicating the head end of the data row, the start code being located upstream of the data row and having a predetermined logical structure represented by plural bits (e.g., eight bits), a stop code for indicating the tail end of the data row, the stop code being disposed downstream of the data row and likewise having a predetermined logical structure (which is different from the logical structure of the start code) represented by plural bits (e.g., eight bits), and an error check code independently generated at each node controller for the purpose of searching for an occurrence of error between respective ports (between respective node controllers), the error check code being disposed downstream of the stop code to be added as a code signal having a predetermined number of bits (e.g., 16 bits). The main controller 30 and the node controllers 41 to 4n are informed of the presence of data (data row) based on detection of the start code and the stop code. In addition, the main controller 30 and the node controllers 41 to 4n are informed of an occurrence of error based on inspection of the error check code (to be conducted in accordance with a CRC checking process, a vertical/horizontal parity checking process or the like process).
With such latter-described apparatus for carrying out serial control, signals are transmitted between the main controller and the node controllers, whereby transmission of data from the main controller to the node controllers and vice versa, as well as error checking, can effectively be accomplished without fail. However, when an occurrence of error is confirmed and transmitted to a node controller at the next stage or the central main controller 30, the following problems arise depending on the type signals which are transmitted.
The problems will be exemplified below with reference to FIG. 10 and FIG. 11 on the assumption that an error occurs during transmission of signals (data) between a node controller 41 and a node controller 42. Incidentally, T.sub.00, T.sub.01, T.sub.11, T.sub.12 and T.sub.22 in FIG. 11 represent a time, respectively.
(1) Case where a series of signals S0 to Sn are transmitted between respective node controllers with time delay equivalent to a length of the respective signals in each node controller, i.e, in the example shown in FIG. 11, the respective times as noted above are set in accordance with a relationship represented by T00&lt;T01=T11 T12=T21&lt;T22
In this case, e.g., a signal S1 is fully inputted into the node controller 42 from the node controller 41 and it is then delivered to a node controller 43 as a signal S3. Therefore, in this case, the node controller 41 can check an occurrence of error between the node controller 41 and the node controller 42 without fail. Thus, it is possible to undertake a processing as represented, e.g., by the wording "stop outputting of signals", the wording "send a signal for informing an occurrence of error" or the like wording. In this case, however, data delay equivalent to a time (T.sub.01 -T.sub.00) is caused between all the node controllers, resulting in substantially reduced data transmission efficiency.
(2) Case where a series of signals S0 to Sn are transmitted without time delay at each node controller, i.e., in the example shown in FIG. 11, the respective times noted above are set in accordance with a relationship represented by T00=T11=T21 or T11&lt;T01 and T21&lt;T12
In this case, e.g., the node controller 42 outputs a signal S2 to the node controller 43 without any interruption, before a signal S1 outputted from the node controller 41 is fully inputted into the node controller 42. Therefore, in this case, the aforementioned time delay can be reduced. On the other hand, when the node controller 42 checks and confirms an occurrence of error between the node controller 41 and the node controller 42, this means that inputting of the signal S2 outputted from the node controller 43 into the node controller 42 has been started or completed. After all, information of the occurrence of error to any one of node controllers located downstream of the node controller 43 can not be carried out satisfactorily. Consequently, there is a high level of possibility that actuators arranged corresponding to node controllers located downstream of the node controller 43 may operate incorrectly or sensors arranged corresponding to any one of node controllers located upstream of the node controller 41 may provide incorrect information.
The present invention has been made with the foregoing background in mind and its object resides in providing an apparatus for carrying out serial control wherein an occurrence of error can reliably be informed to a node controller at the next stage as well as a main controller without reduction of an efficiency for transmitting data.